#include "../../chip/m3281/chip_m3281.h"
#include "../board_cfg.h"
#include "tve_hd_setting_half_mode.h"

#if defined(DUAL_VIDEO_OUTPUT_USE_VCAP)
#include "tve_old_cfg_setting_m3606.h"
#endif

#include <sys_config.h>
#include <hld/nim/nim_tuner.h>

BoardCfg board_config;

#define SYS_BOARD_IS_M3606_01V02

static const struct ir_key_map_t	g_itou_key_tab[] =
{
	// ali 60 key remote controller.
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df926d)}, V_KEY_0},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfc837)}, V_KEY_1},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df08f7)}, V_KEY_2},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df8877)}, V_KEY_3},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dff00f)}, V_KEY_4},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df30cf)}, V_KEY_5},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfb04f)}, V_KEY_6},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfd02f)}, V_KEY_7},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df10ef)}, V_KEY_8},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df906f)}, V_KEY_9},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df38c7)}, V_KEY_LEFT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df12ed)}, V_KEY_RIGHT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df22dd)}, V_KEY_UP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfb847)}, V_KEY_DOWN},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df50af)}, V_KEY_MP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df3ac5)}, V_KEY_ENTER},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfd22d)}, V_KEY_P_UP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfe01f)}, V_KEY_P_DOWN},
	//{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f28d7)}, V_KEY_BOOKMARK},
	//{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fa857)}, V_KEY_JUMPMARK},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df827d)}, V_KEY_TEXT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df708f)}, V_KEY_POWER},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df20df)}, V_KEY_PREV},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df0af5)}, V_KEY_NEXT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df629d)}, V_KEY_AUDIO},
#if (ISDBT_CC == 1)
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df807f)}, V_KEY_CC},
#else
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df807f)}, V_KEY_SUBTITLE},
#endif
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df9867)}, V_KEY_SLEEP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfe21d)}, V_KEY_FIND},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfa05f)}, V_KEY_MUTE},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df7a85)}, V_KEY_PAUSE},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfa25d)}, V_KEY_VIDEO_FORMAT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df6897)}, V_KEY_INFOR},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df42bd)}, V_KEY_EXIT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df52ad)}, V_KEY_TVSAT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df02fd)}, V_KEY_TVRADIO},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfc23d)}, V_KEY_FAV},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfa857)}, V_KEY_RECORD},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df18e7)}, V_KEY_PLAY},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df58a7)}, V_KEY_FB},//red
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfd827)}, V_KEY_FF},//green
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df4ab5)}, V_KEY_B_SLOW},//yellow
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfaa55)}, V_KEY_SLOW},//blue
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfe817)}, V_KEY_STOP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df40bf)}, V_KEY_ZOOM},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df00ff)}, V_KEY_EPG},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df2ad5)}, V_KEY_MENU},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfc03f)}, V_KEY_RECALL},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df609f)}, V_KEY_RED},//red
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df7887)}, V_KEY_GREEN},//green
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dff807)}, V_KEY_YELLOW},//yellow
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfba45)}, V_KEY_BLUE},//blue

	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfca35)}, V_KEY_PVR_INFO},
//#ifndef SUPPORT_CAS9
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfb24d)}, V_KEY_FILELIST},
//#endif
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df8a75)}, V_KEY_DVRLIST},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df1ae5)}, V_KEY_USBREMOVE},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df6a95)}, V_KEY_PIP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df9a65)}, V_KEY_PIP_LIST},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df5aa5)}, V_KEY_SWAP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfda25)}, V_KEY_MOVE},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60dfea15)}, V_KEY_REPEATAB},

	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df28d7)}, V_KEY_F_UP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x60df48b7)}, V_KEY_F_DOWN},



	// ali 48 key remote controller.
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fb24d)}, V_KEY_0},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f22dd)}, V_KEY_1},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fa25d)}, V_KEY_2},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f629d)}, V_KEY_3},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fe21d)}, V_KEY_4},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f12ed)}, V_KEY_5},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f926d)}, V_KEY_6},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f52ad)}, V_KEY_7},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fd22d)}, V_KEY_8},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f32cd)}, V_KEY_9},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f9867)}, V_KEY_LEFT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f58a7)}, V_KEY_RIGHT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f18e7)}, V_KEY_UP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fd827)}, V_KEY_DOWN},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f906f)}, V_KEY_MP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807ff20d)}, V_KEY_ENTER},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f28d7)}, V_KEY_P_UP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fa857)}, V_KEY_P_DOWN},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f28d7)}, V_KEY_BOOKMARK},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fa857)}, V_KEY_JUMPMARK},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fc837)}, V_KEY_TEXT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fc03f)}, V_KEY_POWER},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f6897)}, V_KEY_PREV},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fe817)}, V_KEY_NEXT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f40bf)}, V_KEY_AUDIO},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fd02f)}, V_KEY_TIMER},
#if (ISDBT_CC == 1)
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f50af)}, V_KEY_CC},
#else
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f50af)}, V_KEY_SUBTITLE},
#endif
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fb04f)}, V_KEY_LIST},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807ff00f)}, V_KEY_SLEEP},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f609f)}, V_KEY_FIND},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f30cf)}, V_KEY_MUTE},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fb847)}, V_KEY_PAUSE},
#if (ISDBT_CC == 1)
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x00000156)}, V_KEY_CC},
#else
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x00000156)}, V_KEY_SUBTITLE},
#endif
#ifdef HDTV_SUPPORT
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fa05f)}, V_KEY_VIDEO_FORMAT},
#else
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fa05f)}, V_KEY_HELP},
#endif
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f20df)}, V_KEY_INFOR},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f48b7)}, V_KEY_EXIT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f00ff)}, V_KEY_TVSAT},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f807f)}, V_KEY_TVRADIO},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f10ef)}, V_KEY_FAV},
#ifdef DVR_PVR_SUPPORT
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f38c7)}, V_KEY_RECORD},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f7887)}, V_KEY_PLAY},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f02fd)}, V_KEY_FB},//red
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f827d)}, V_KEY_FF},//green
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f42bd)}, V_KEY_B_SLOW},//yellow
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fc23d)}, V_KEY_SLOW},//blue
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807ff807)}, V_KEY_STOP},
#endif
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fe01f)}, V_KEY_LANGUAGE},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f708f)}, V_KEY_ZOOM},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f08f7)}, V_KEY_EPG},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f8877)}, V_KEY_MENU},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f728d)}, V_KEY_RECALL},
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f02fd)}, V_KEY_RED},//red
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f827d)}, V_KEY_GREEN},//green
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807f42bd)}, V_KEY_YELLOW},//yellow
	{{PAN_KEY_TYPE_REMOTE, PAN_KEY_PRESSED, 0, SET_IRCODE(0x807fc23d)}, V_KEY_BLUE},//blue

	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF0044)}, V_KEY_POWER },
	//{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF0056)}, V_KEY_ENTER },
	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF0074)}, V_KEY_VIDEO_FORMAT},
	//{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF006e)}, V_KEY_MENU },
	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF0064)}, V_KEY_LEFT },
	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF0054)}, V_KEY_UP },
	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF005c)}, V_KEY_DOWN },
	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF006c)}, V_KEY_RIGHT },
	{{PAN_KEY_TYPE_PANEL, PAN_KEY_PRESSED, 0, SET_IRCODE(0xFFFF004c)}, V_KEY_TVRADIO},
};

IR_Key_Map_t ir_key_maps[] =
{
    {ROCK00,IRP_NEC,0x807f},
};



static struct pan_hw_info pan_hw_info =
{
	0,				/* type_kb : 2; Key board (array) type */
	1,				/* type_scan : 1; 0: Slot scan, 1: Shadow scan */
	1,				/* type_key: 1; Key exit or not */
	1,				/* type_irp: 3; 0: not IRP, 1: NEC, 2: LAB */
	0,				/* type_mcu: 1; MCU exit or not */
	4,				/* num_com: 4; Number of com PIN, 0 to 8 */
	1,				/* Position of colon flag, 0 to 7 */
	1,				/* num_scan: 2; Number of scan PIN, 0 to 2 */
	0,				/* rsvd_bits:6; Reserved bits */
	0,              /* rsvd byte for align pan_info */
	{0, HAL_GPIO_O_DIR, 127},		/* LATCH PIN */
	{0, HAL_GPIO_O_DIR, 	127},		/* CLOCK PIN */
	{1, HAL_GPIO_O_DIR, 	127},		/* DATA PIN */
	{{0, HAL_GPIO_I_DIR, 	127},		/* SCAN1 PIN */
	{0, HAL_GPIO_I_DIR, 127}},		/* SCAN2 PIN */
	{{0, HAL_GPIO_O_DIR, 	127},		/* COM1 PIN */
	{0, HAL_GPIO_O_DIR, 	127},		/* COM2 PIN */
	{0, HAL_GPIO_O_DIR, 	127},		/* COM3 PIN */
	{0, HAL_GPIO_O_DIR, 	127},		/* COM4 PIN */
	{0, HAL_GPIO_O_DIR, 127},		/* COM5 PIN */
	{0, HAL_GPIO_O_DIR, 127},		/* COM6 PIN */
	{0, HAL_GPIO_O_DIR, 127},		/* COM7 PIN */
	{0, HAL_GPIO_O_DIR, 127}},		/* COM8 PIN */
	{{0, HAL_GPIO_O_DIR, 	127},		/* POWER PIN */
	{1, HAL_GPIO_O_DIR, 	127},		/* LOCK PIN */
	{0, HAL_GPIO_O_DIR, 127},		/* Extend function LBD */
	{0, HAL_GPIO_O_DIR, 127}},		/* Extend function LBD */
    {0, HAL_GPIO_O_DIR, 127},       /* rsvd extend function LBD */        
	300,							/* Intv repeat first */
	250,							/* Intv repeat */
	350,							    /* Intv release, 0: disable release key */
	NULL,	 	 	 	 	 	 	/* hook_scan() callback */
	NULL,	 	 	 	 	 	 	/* hook_show() callback */
	0,	 	 	 	 	 	 	/* p_seg */
};
#define bitmap_list				NULL
#define bitmap_list_num		0
struct pan_configuration pan_config = {&pan_hw_info, bitmap_list_num, bitmap_list};


static PinMuxInfo pin_mux_array[] = 
{
    {I2C_SEL,               1},
    {I2C2_SEL,             1},
    {CI_SEL,                1},
    {UART_SEL,          1},
    {SMCARD_SEL2,       1},    
#ifdef DUAL_ENABLE2
    {UART2_TX_SEL,          1},
#endif
};
/*
//shi add for pin mux
#ifdef  _CAS9_CA_ENABLE_
	data = *((unsigned long *)0xb8000088);

	data |= (1 << 24);  // I2C0
	data |= (1 << 25);  // I2C1 BGA
	//data |= (1 << 26);  // I2C1 QFP
	//data |= (1 << 27);  // I2C1 216
	data |= (1 << 0);   // for CI
	data |= (1 << 1);   // for CI
	data |= (1 << 2);   // for TSI SPI
	data |= (1 << 14);//smc
	*((unsigned long *)0xb8000088) = data;

	data = *((unsigned long *)0xb800008C);
	data |= (1 << 2);   // TSI_SPI sel
	data |= (1 << 3);   // TSI_SPI2 sel
	data |= (1 << 31);  // BGA I2S output sel
	//data |= (1 << 30);  // QFP I2S output sel
	//data |= (1 << 29); // 216 I2S output sel
	//data |= (1 << 28);  // I2S input sel
	*((unsigned long *)0xb800008C) |= data;
	osal_delay_ms(1000);
#endif
*/



static GpioInfo gpio_array[] = 
{    
    {1, HAL_GPIO_O_DIR, 45},        //SYS_I2C_SDA
    {1, HAL_GPIO_O_DIR, 44},        //SYS_I2C_SCL    
    
    {1, HAL_GPIO_O_DIR, 21},        //snd mute set 1
    {0, HAL_GPIO_O_DIR, 107},      //power off
  
    {1, HAL_GPIO_O_DIR, 12},  // SCART tv_mode
    {1, HAL_GPIO_O_DIR, 11}, //scart 16/9EN
    {0, HAL_GPIO_O_DIR, 10}, //TV STANDBY

    {1, HAL_GPIO_O_DIR, 6}, //lnb
#ifndef POWER_ENJ_DEFAULT
    {0, HAL_GPIO_O_DIR, 20}, //SMC 5V/3.3V switch   
#else
	{1, HAL_GPIO_O_DIR, 20}, //SMC 5V/3.3V switch  
#endif  
};

enum{
	GPIO_I2C0_SDA_INDEX=0,
	GPIO_I2C0_SCL_INDEX,

	SYS_MUTE_INDEX,
	SYS_POWER_INDEX,
	
	SCART_TV_FB_GPIO_INDEX ,
	SCART_ASPACT_GPIO_INDEX ,
	SCART_TVSTANDBY_GPIO_INDEX ,	

	LNB_GPIO_CUT_POWER,

	SYS_SMC_SWITCH,
};

#define MEM_GPIO_ENABLED    1

FrontEndCfg front_end[2];

#ifdef DVBS_SUPPORT
extern INT32 nim_s3281_dvbs_attach (struct QPSK_TUNER_CONFIG_API * ptrQPSK_Tuner);
FrontEndCfg* front_end_s_cfg(UINT8 tuner_id)
{
    struct QPSK_TUNER_CONFIG_API* qpsk_tuner;
    FrontEndCfg* cfg;
    UINT32 data_long=0x00;
    if(tuner_id > 1)
        return NULL;
    cfg = &front_end[tuner_id];
    MEMSET(cfg, 0, sizeof(FrontEndCfg));
    
    cfg->front_end_type = FRONTEND_TYPE_S;
    cfg->sat_id = 2;
    cfg->lnb_power = &gpio_array[LNB_GPIO_CUT_POWER];
    cfg->lnb_short_det = NULL;
	
    if(tuner_id == 0)
    	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET0];
    else 
	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET1];
	
   // if(tuner_id == 0)
        cfg->nim_name = "NIM_S3501_0";
   // else
   //     cfg->nim_name = "NIM_S3501_1";
        

    cfg->tsi_cfg.tsi_attr = 0x83;     //shi modify for 3603 
    if(tuner_id == 0)
    {
        cfg->tsi_cfg.tsi_select = TSI_DMX_0;
        cfg->tsi_cfg.tsi_id = TSI_SPI_0 ;
    }
    else
    {
        cfg->tsi_cfg.tsi_select = TSI_DMX_1;
        cfg->tsi_cfg.tsi_id = TSI_SPI_1 ;
    }

    cfg->tsi_cfg.tsi_spi_tsg_attr = 0x83;
    cfg->nim_config.s_cfg.tsi_id_m3501a = TSI_SSI_0;
    cfg->nim_config.s_cfg.tsi_attr_m3501a = 0x8b;	

    cfg->nim_config.s_cfg.attach = nim_s3281_dvbs_attach;

	
    qpsk_tuner = &cfg->nim_config.s_cfg.qpsk_tuner;
    MEMSET(qpsk_tuner,0,sizeof(struct QPSK_TUNER_CONFIG_API));
	qpsk_tuner->nim_Tuner_Init = nim_ix2410_init;
	qpsk_tuner->nim_Tuner_Control = nim_ix2410_control;
	qpsk_tuner->nim_Tuner_Status	= nim_ix2410_status;
	qpsk_tuner->config_data.Recv_Freq_Low = 900;
	qpsk_tuner->config_data.Recv_Freq_High = 2146;    
	qpsk_tuner->config_data.Ana_Filter_BW = 30000;
	qpsk_tuner->config_data.Connection_config = 0x00;
	qpsk_tuner->config_data.QPSK_Config = 0x10;
	qpsk_tuner->config_data.AGC_Threshold_1 = 0x0F;
	qpsk_tuner->config_data.AGC_Threshold_2 = 0x15;
	qpsk_tuner->tuner_config.wTuner_Crystal = 4000;
	qpsk_tuner->tuner_config.cTuner_Out_S_D_Sel = 1;
	qpsk_tuner->tuner_config.i2c_type_id = I2C_TYPE_SCB0;
	qpsk_tuner->tuner_config.cTuner_Base_Addr = 0xc0;      //SYS_TUN_BASE_ADDR;

    // Nim config begin
    	// dvbs mode select
	data_long=(*(volatile UINT32 *)(0xb80000f8)); // config demod mod 
	data_long = data_long & 0xff9fffff;
	data_long = data_long | 0x00400000;		
	(*(volatile UINT32 *)(0xb80000f8))= data_long;

	
	data_long=(*(volatile UINT32 *)(0xb80000f0)); // config demod agc
	data_long = data_long | 0x02000000;		
	(*(volatile UINT32 *)(0xb80000f0))= data_long;

	data_long=(*(volatile UINT32 *)(0xb80000fc)); // config demod clk
	// 90MHz
	//data_long = data_long & 0xfffffffe;
	//data_long = data_long | 0x00000882;		
	// 98MHz
	data_long = data_long | 0x00000883;		
	(*(volatile UINT32 *)(0xb80000fc))= data_long;
	
    //Nim config end
    

    return cfg;
}
#endif

#ifdef ISDBT_SUPPORT
extern INT32 f_dib8000_attach(struct COFDM_TUNER_CONFIG_API *ptrCOFDM_Tuner);

FrontEndCfg* front_end_isdbt_cfg(UINT8 tuner_id)
{
    struct COFDM_TUNER_CONFIG_API*  isdbt_tuner;
    FrontEndCfg* cfg;
    if(tuner_id > 1)
        return NULL;
    
    cfg = &front_end[tuner_id];
    MEMSET(cfg, 0, sizeof(FrontEndCfg));
    cfg->front_end_type = FRONTEND_TYPE_T;    
    cfg->sat_id = 1;
    cfg->lnb_power = NULL;
    cfg->lnb_short_det = NULL;
    cfg->nim_reset = NULL;
    //if(tuner_id == 0)
        cfg->nim_name = "NIM_DIB8000_0";
   // else
   //     cfg->nim_name = "NIM_DIB8000_1";

   cfg->tsi_cfg.tsi_id = TSI_SPI_1;  //shi  TSI_SSI_1
   cfg->tsi_cfg.tsi_attr = 0x87;
   if(tuner_id == 0)
       cfg->tsi_cfg.tsi_select = TSI_TS_A;
   else
       cfg->tsi_cfg.tsi_select = TSI_TS_B;
   cfg->tsi_cfg.tsi_spi_tsg_attr = 0x83;
   cfg->nim_config.t_cfg.attach = f_dib8000_attach;
   isdbt_tuner = &cfg->nim_config.t_cfg.cofdm_tuner;
   isdbt_tuner->ext_dm_config.i2c_type_id = I2C_TYPE_SCB0;//I2C_TYPE_SCB1;
   isdbt_tuner->ext_dm_config.i2c_base_addr = 0;//0xC0;
   isdbt_tuner->tuner_config.i2c_type_id = I2C_TYPE_SCB0;//I2C_TYPE_SCB1;
   isdbt_tuner->tuner_config.cTuner_Base_Addr = 0;
    // Work around to Enable SSI1_2 data swap
    //*((volatile UINT8 *)(0xb801a00b)) = (*(volatile UINT8  *)(0xb801a00b)) | 0x10;   
   cfg->is_isdbt = 1;
   return cfg;
}
#endif

#ifdef DVBT_SUPPORT
#define M3100_REV_ID        4
extern INT32 i2c_scb_write(UINT32 id, UINT8 slv_addr, UINT8 *data, int len);
extern INT32 i2c_scb_read(UINT32 id,UINT8 slv_addr, UINT8 *data, int len);	//51117-01Angus
extern INT32 i2c_scb_write_read(UINT32 id, UINT8 slv_addr, UINT8 *data, int wlen, int rlen);
extern INT32 i2c_gpio_read(UINT32 id, UINT8 slv_addr, UINT8 *data, int len);
extern INT32 i2c_gpio_write(UINT32 id, UINT8 slv_addr, UINT8 *data, int len);
extern INT32 nim_m3101_dev_attach_ext(char *name, PCOFDM_TUNER_CONFIG_API pConfig);

#if (SYS_DVBT_DEMO_MODULE == MXL101)
extern INT32 f_MXL101_attach(char *name,struct COFDM_TUNER_CONFIG_API *ptrCOFDM_Tuner);
FrontEndCfg* front_end_t_cfg(UINT8 tuner_id)
{
     struct COFDM_TUNER_CONFIG_API*  t_tuner;
     FrontEndCfg* cfg;
     if(tuner_id > 1)
         return NULL;
     
     cfg = &front_end[tuner_id];
     MEMSET(cfg, 0, sizeof(FrontEndCfg));
     cfg->front_end_type = FRONTEND_TYPE_T;    
     cfg->sat_id = 1;
     cfg->lnb_power = NULL;
     cfg->lnb_short_det = NULL;
      if(tuner_id == 0)
    	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET0];
    else 
	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET1];
     //if(tuner_id == 0)
         cfg->nim_name = "NIM_COFDM_0";
    // else
    //     cfg->nim_name = "NIM_COFDM_1";

    cfg->tsi_cfg.tsi_id = TSI_SPI_1;
    cfg->tsi_cfg.tsi_attr = 0x87;
    if(tuner_id == 0)
       cfg->tsi_cfg.tsi_select = TSI_TS_A;
    else
       cfg->tsi_cfg.tsi_select = TSI_TS_B;
    cfg->tsi_cfg.tsi_spi_tsg_attr = 0x83;   
    cfg->nim_config.t_cfg.attach_with_name = f_MXL101_attach;
    t_tuner = &cfg->nim_config.t_cfg.cofdm_tuner;
    
    t_tuner->ext_dm_config.i2c_type_id = I2C_TYPE_SCB0;
    t_tuner->ext_dm_config.i2c_base_addr = 0xC6;
    t_tuner->ext_dm_config.lock_polar_reverse = 1;
    t_tuner->ts_mode = NIM_COFDM_TS_SPI_8B;    
    t_tuner->config_mode = 1;
    cfg->is_isdbt = 0;
    return cfg;
}
#else
FrontEndCfg* front_end_t_cfg(UINT8 tuner_id)
{
     struct COFDM_TUNER_CONFIG_API*  t_tuner;
     FrontEndCfg* cfg;
     if(tuner_id > 1)
         return NULL;
     
     cfg = &front_end[tuner_id];
     MEMSET(cfg, 0, sizeof(FrontEndCfg));
     cfg->front_end_type = FRONTEND_TYPE_T;    
     cfg->sat_id = 1;
     cfg->lnb_power = NULL;
     cfg->lnb_short_det = NULL;
	 
       if(tuner_id == 0)
    	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET0];
    else 
	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET1];
	
     //if(tuner_id == 0)
         cfg->nim_name = "NIM_COFDM_0";
    // else
    //     cfg->nim_name = "NIM_COFDM_1";

    cfg->tsi_cfg.tsi_id = TSI_SPI_1; //shi TSI_SPI_1,TSI_SSI_1
    cfg->tsi_cfg.tsi_attr = 0x83;
    if(tuner_id == 0)
       cfg->tsi_cfg.tsi_select = TSI_TS_A;
    else
       cfg->tsi_cfg.tsi_select = TSI_TS_B;
    cfg->tsi_cfg.tsi_spi_tsg_attr = 0x83;   
    cfg->nim_config.t_cfg.attach_with_name = nim_m3101_dev_attach_ext;
    t_tuner = &cfg->nim_config.t_cfg.cofdm_tuner;
    
    t_tuner->config_data.Connection_config = 0x00; //no I/Q swap.
    t_tuner->config_data.Cofdm_Config = 0x03;//low-if, dirct , if-enable.
    t_tuner->config_data.AGC_REF = 0x53;
    t_tuner->config_data.IF_AGC_MAX = 0xff;
    t_tuner->config_data.IF_AGC_MIN = 0x00;

    t_tuner->nim_Tuner_Init = tun_mxl5005_init;
    t_tuner->nim_Tuner_Control = tun_mxl5005_control;
    t_tuner->nim_Tuner_Status =  tun_mxl5005_status;
    t_tuner->tuner_config.cTuner_Crystal = 16; // Unit: MHz
    t_tuner->tuner_config.wTuner_IF_Freq = 4570; //36170
    t_tuner->tuner_config.cTuner_AGC_TOP = 252; //Special for MaxLiner
    t_tuner->tuner_config.cChip = Tuner_Chip_MAXLINEAR; //Tuner_Chip_PHILIPS
    t_tuner->tuner_config.Tuner_Write = i2c_scb_write;
    t_tuner->tuner_config.Tuner_Read = i2c_scb_read;
    
    t_tuner->tuner_config.i2c_type_id = I2C_TYPE_SCB0;
    t_tuner->tuner_config.cTuner_Base_Addr = 0xc6;
    t_tuner->ext_dm_config.i2c_type_id = I2C_TYPE_SCB0;
    t_tuner->ext_dm_config.i2c_base_addr = 0x42;
    t_tuner->ts_mode = NIM_COFDM_TS_SPI_8B;  //NIM_COFDM_TS_SPI_8B  ,NIM_COFDM_TS_SSI
    t_tuner->tuner_type = MXL5005;
    t_tuner->rev_id = M3100_REV_ID; // cofdm mode can't read ver id from register
    t_tuner->config_mode = 1;
    t_tuner->work_mode = NIM_COFDM_ONLY_MODE;
    cfg->is_isdbt = 0;
    return cfg;
}

#endif
#endif
#if 0
FrontEndCfg* front_end_isdbt_cfg(UINT8 tuner_id)
{
    struct COFDM_TUNER_CONFIG_API*  isdbt_tuner;
    FrontEndCfg* cfg;
    if(tuner_id > 1)
        return NULL;
    
    cfg = &front_end[tuner_id];
    MEMSET(cfg, 0, sizeof(FrontEndCfg));
    cfg->front_end_type = FRONTEND_TYPE_T;
    cfg->lnb_power = NULL;
    cfg->lnb_short_det = NULL;
    cfg->nim_reset = NULL;
    //if(tuner_id == 0)
        cfg->nim_name = "NIM_TC90517_0";
   // else
   //     cfg->nim_name = "NIM_DIB8000_1";

   cfg->tsi_cfg.tsi_id = TSI_SSI_1;
   cfg->tsi_cfg.tsi_attr = 0x87;
   if(tuner_id == 0)
       cfg->tsi_cfg.tsi_select = TSI_TS_A;
   else
       cfg->tsi_cfg.tsi_select = TSI_TS_B;
   cfg->tsi_cfg.tsi_spi_tsg_attr = 0x83;
   cfg->nim_config.t_cfg.attach = f_TC90517_attach;
   isdbt_tuner = &cfg->nim_config.t_cfg.cofdm_tuner;
   isdbt_tuner->ext_dm_config.i2c_type_id = I2C_TYPE_SCB0;//I2C_TYPE_SCB1;
   isdbt_tuner->ext_dm_config.i2c_base_addr = 0xC0;
   isdbt_tuner->tuner_config.i2c_type_id = I2C_TYPE_SCB0;//I2C_TYPE_SCB1;
   isdbt_tuner->tuner_config.cTuner_Base_Addr = 0xC0;

    isdbt_tuner->nim_Tuner_Init = tun_tda18212_init;
    isdbt_tuner->nim_Tuner_Control = tun_tda18212_control;
    isdbt_tuner->nim_Tuner_Status = tun_tda18212_status;
    isdbt_tuner->tuner_config.cTuner_Crystal = 16000;    //khz
    isdbt_tuner->tuner_config.cTuner_Ref_DivRatio = 128;
    isdbt_tuner->tuner_config.wTuner_IF_Freq = 4000;
    isdbt_tuner->tuner_config.cTuner_AGC_TOP = 2;// from 0~7 //can be setted by COFDM, ex.disable RF Auto-AGC
    isdbt_tuner->tuner_config.cTuner_Step_Freq = 125;
    isdbt_tuner->tuner_config.cChip = Tuner_Chip_QUANTEK;
    isdbt_tuner->tuner_config.Tuner_Write = i2c_scb_write; //can be setted by COFDM
    isdbt_tuner->tuner_config.Tuner_Read = i2c_scb_read;   //can be setted by COFDM
    isdbt_tuner->tuner_config.Tuner_Write_Read = i2c_scb_write_read;
   
    // Work around to Enable SSI1_2 data swap
    //*((volatile UINT8 *)(0xb801a00b)) = (*(volatile UINT8  *)(0xb801a00b)) | 0x10;   
   return cfg;
}
#endif


#ifdef DVBC_SUPPORT
//3202 fullnim(alps) 
INT32 nim_s3281_dvbc_attach(struct QAM_TUNER_CONFIG_API * ptrQAM_Tuner);
enum DVBC_MODE_TYPE
{
	DVBC_MODE_J83AC = 0,
	DVBC_MODE_J83B = 1,
		
};
extern void m32_pin_mux_set_qam_select(UINT8 dvbc_mode);
void front_end_c_get_QAM_config(UINT8 dvbc_mode,UINT32 nim_clk,struct DEMOD_CONFIG_ADVANCED* pDemod_config)
{	
	if(dvbc_mode == DVBC_MODE_J83B)
	{
		pDemod_config->qam_buffer_len= __MM_NIM_BUFFER_LEN;	
		pDemod_config->qam_buffer_addr=__MM_NIM_BUFFER_ADDR;
		pDemod_config->qam_config_advanced = NIM_DVBC_J83B_MODE | nim_clk;  // j83ac, 54m sampleclk/dspclk
	}
	else if(dvbc_mode == DVBC_MODE_J83AC)
	{
		pDemod_config->qam_buffer_len= 0x00;	
		pDemod_config->qam_buffer_addr=0x00;
		pDemod_config->qam_config_advanced = NIM_DVBC_J83AC_MODE |nim_clk;  // j83ac, 54m sampleclk/dspclk
	}
	m32_pin_mux_set_qam_select(dvbc_mode);
}

FrontEndCfg* front_end_c_cfg(UINT8 tuner_id)
{    
    struct QAM_TUNER_CONFIG_API*  c_tuner;
    UINT8 bI2cType = I2C_TYPE_SCB0;
    FrontEndCfg* cfg;
    UINT32 data_long=0x00;
    UINT32 mode_value=DVBC_MODE_J83AC;
    UINT32 mode_sub=0x00;
    if(tuner_id > 1)
     return NULL;

    cfg = &front_end[tuner_id];
    MEMSET(cfg, 0, sizeof(FrontEndCfg));
    cfg->front_end_type = FRONTEND_TYPE_C;    
    cfg->sat_id = 1;
    cfg->lnb_power = NULL;
    cfg->lnb_short_det = NULL;    
    cfg->is_isdbt = 0;
    
    if(tuner_id == 0)
        cfg->nim_name = "NIM_S3202_0";
    else
        cfg->nim_name = "NIM_S3202_1";

    
    if(tuner_id == 0)
    	cfg->nim_reset = NULL;// &gpio_array[SYS_NIM_RESET0];
    else 
	cfg->nim_reset = NULL;//&gpio_array[SYS_NIM_RESET1];

    if(tuner_id == 0)
        cfg->tsi_cfg.tsi_id = TSI_SPI_0;
    else      
       cfg->tsi_cfg.tsi_id = TSI_SPI_1;
    
    cfg->tsi_cfg.tsi_attr = 0x83;
    
    if(tuner_id == 0)
       cfg->tsi_cfg.tsi_select = TSI_TS_A;
    else
       cfg->tsi_cfg.tsi_select = TSI_TS_B;
    
    cfg->tsi_cfg.tsi_spi_tsg_attr = 0x83;


    /*config tuner S3202 START ************************************************************************/
    
    cfg->nim_config.c_cfg.attach = nim_s3281_dvbc_attach;
    c_tuner = &cfg->nim_config.c_cfg.qam_tuner;

    c_tuner->tuner_config_data.cTuner_Tsi_Setting = NIM_0_SPI_0;

#if 0  //1 DCT70707
//config for tuner DCT70707
c_tuner->tuner_config_data.RF_AGC_MAX = 0xBA;		
c_tuner->tuner_config_data.RF_AGC_MIN = 0x2A;		
c_tuner->tuner_config_data.IF_AGC_MAX = 0xFE;		
c_tuner->tuner_config_data.IF_AGC_MIN = 0x01;		
c_tuner->tuner_config_data.AGC_REF 			= 0x80;			
c_tuner->tuner_config_ext.cTuner_special_config = 0x01; 
// RF AGC is disabled		
c_tuner->tuner_config_ext.cChip				= Tuner_Chip_NXP;		
c_tuner->tuner_config_ext.cTuner_AGC_TOP	= 1;//7; /*1 for single AGC, 7 for dual AGC */		
c_tuner->tuner_config_ext.cTuner_Base_Addr	= 0xc2;		
c_tuner->tuner_config_ext.cTuner_Crystal		= 4;		
c_tuner->tuner_config_ext.cTuner_Ref_DivRatio	= 64; 		
c_tuner->tuner_config_ext.cTuner_Step_Freq	= 62.5;		
//(Ref_divRatio*Step_Freq)=(80*50)=(64*62.5)=(24*166.7)		
c_tuner->tuner_config_ext.wTuner_IF_Freq		= 36000; //5070; //4063; //5070;//36000;
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83AC		= 36000;
//ptrQAM_Tuner->tuner_config_ext.cTuner_Charge_Pump= 0;  		
c_tuner->tuner_config_ext.i2c_type_id 			= I2C_TYPE_SCB1;//I2C_TYPE_SCB0;		
extern INT32 tun_dct70701_init(UINT32 * ptrTun_id, struct QAM_TUNER_CONFIG_EXT * ptrTuner_Config);		
extern INT32 tun_dct70701_control(UINT32 Tun_id, UINT32 freq, UINT32 sym, UINT8 AGC_Time_Const, UINT8 _i2c_cmd);		
extern INT32 tun_dct70701_status(UINT32 Tun_id, UINT8 *lock);		
c_tuner->nim_Tuner_Init = tun_dct70701_init;		
c_tuner->nim_Tuner_Control = tun_dct70701_control;		
c_tuner->nim_Tuner_Status = tun_dct70701_status;
c_tuner->tuner_config_ext.i2c_type_id = bI2cType;
front_end_c_get_QAM_config(mode_value,NIM_SAMPLE_CLK_54M,&(c_tuner->dem_config_advanced));
#else  //1RT810 /RT820
//config for tuner RT810
c_tuner->tuner_config_data.RF_AGC_MAX = 0xBA;		
c_tuner->tuner_config_data.RF_AGC_MIN = 0x2A;		
c_tuner->tuner_config_data.IF_AGC_MAX = 0xFE;		
c_tuner->tuner_config_data.IF_AGC_MIN = 0x01;		
c_tuner->tuner_config_data.AGC_REF 			= 0x80;			
c_tuner->tuner_config_ext.cTuner_special_config = 0x01; 
// RF AGC is disabled		
c_tuner->tuner_config_ext.cChip				= Tuner_Chip_NXP;		
c_tuner->tuner_config_ext.cTuner_AGC_TOP	= 1;//7; /*1 for single AGC, 7 for dual AGC */		
c_tuner->tuner_config_ext.cTuner_Base_Addr	= 0x34;		
c_tuner->tuner_config_ext.cTuner_Crystal		= 4;		
c_tuner->tuner_config_ext.cTuner_Ref_DivRatio	= 64; 		
c_tuner->tuner_config_ext.cTuner_Step_Freq	= 62.5;		
//(Ref_divRatio*Step_Freq)=(80*50)=(64*62.5)=(24*166.7)		
#if(SYS_TUN_MODULE == RT820)
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83A=5070;
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83B=4080;
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83C=4080;
#else
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83A=5057;
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83B=4067;
c_tuner->tuner_config_ext.wTuner_IF_Freq_J83C=4067;
#endif
if(mode_value == DVBC_MODE_J83AC)
{
	c_tuner->tuner_config_ext.wTuner_IF_J83AC_type=mode_sub;
	c_tuner->tuner_config_ext.wTuner_IF_Freq		= c_tuner->tuner_config_ext.wTuner_IF_Freq_J83A;
	if(mode_sub==0x01)
	c_tuner->tuner_config_ext.wTuner_IF_Freq		= c_tuner->tuner_config_ext.wTuner_IF_Freq_J83C;
}
else
	c_tuner->tuner_config_ext.wTuner_IF_Freq		= c_tuner->tuner_config_ext.wTuner_IF_Freq_J83B;
c_tuner->tuner_config_ext.cTuner_reopen=0x00;
c_tuner->tuner_config_ext.i2c_type_id = bI2cType;

#if(SYS_TUN_MODULE == RT820)
extern INT32 tun_rt820_init(UINT32 * ptrTun_id, struct QAM_TUNER_CONFIG_EXT * ptrTuner_Config);		
extern INT32 tun_rt820_control(UINT32 Tun_id, UINT32 freq, UINT32 sym, UINT8 AGC_Time_Const, UINT8 _i2c_cmd);		
extern INT32 tun_rt820_status(UINT32 Tun_id, UINT8 *lock);		
c_tuner->nim_Tuner_Init = tun_rt820_init;		
c_tuner->nim_Tuner_Control = tun_rt820_control;		
c_tuner->nim_Tuner_Status = tun_rt820_status;
#else
extern INT32 tun_rt810_init(UINT32 * ptrTun_id, struct QAM_TUNER_CONFIG_EXT * ptrTuner_Config);		
extern INT32 tun_rt810_control(UINT32 Tun_id, UINT32 freq, UINT32 sym, UINT8 AGC_Time_Const, UINT8 _i2c_cmd);		
extern INT32 tun_rt810_status(UINT32 Tun_id, UINT8 *lock);		
c_tuner->nim_Tuner_Init = tun_rt810_init;		
c_tuner->nim_Tuner_Control = tun_rt810_control;		
c_tuner->nim_Tuner_Status = tun_rt810_status;
#endif
front_end_c_get_QAM_config(mode_value,NIM_SAMPLE_CLK_27M,&(c_tuner->dem_config_advanced));
if(mode_value == DVBC_MODE_J83AC)
{
	c_tuner->tuner_config_ext.cTuner_freq_param=0x09;//DVBC_MODE_J83AC ,  0x0c(J83B)
	if(mode_sub==0x01)
		c_tuner->tuner_config_ext.cTuner_freq_param=0x0c;
}
else
	c_tuner->tuner_config_ext.cTuner_freq_param=0x0c;

#endif

//DVBC clock 54M/27M mode select
if((NIM_SAMPLE_CLK_54M & c_tuner->dem_config_advanced.qam_config_advanced) ==NIM_SAMPLE_CLK_54M)
{
	data_long=(*(volatile UINT32 *)(0xB80000f8));// config clk mod 
	data_long = data_long & 0xff7fffff;
	(*(volatile UINT32 *)(0xB80000f8)) = data_long;
	
	data_long=(*(volatile UINT32 *)(0xB80000fc));// config clk mod 
	data_long = data_long & 0xfffff7ff;
	(*(volatile UINT32 *)(0xB80000fc)) = data_long;
}
else
{
	data_long=(*(volatile UINT32 *)(0xB80000f8)); // config clkmod 
	data_long = data_long & 0xff7fffff;
	data_long = data_long | 0x00800000;		
	(*(volatile UINT32 *)(0xB80000f8)) = data_long;
		
	data_long=(*(volatile UINT32 *)(0xB80000fc));// config clk mod 
	data_long = data_long & 0xfffffcf3;
	data_long = data_long | 0x00000c70;			
	(*(volatile UINT32 *)(0xB80000fc)) = data_long;
}
// IF-AGC out enable and RF-AGC out disable
data_long=(*(volatile UINT32 *)(0xB80000f0));
data_long = data_long & 0xff7fffff;
data_long = data_long | 0x00801000;	
(*(volatile UINT32 *)(0xB80000f0)) = data_long;

 /* config for tuner TDA18250
    c_tuner->tuner_config_data.RF_AGC_MAX = 0xBA;
    c_tuner->tuner_config_data.RF_AGC_MIN = 0x2A;
    c_tuner->tuner_config_data.IF_AGC_MAX = 0xFF;
    c_tuner->tuner_config_data.IF_AGC_MIN = 0x00;
    //trueve 20081224, update according to Program guide 20081223 by Joey.	
    c_tuner->tuner_config_data.AGC_REF = 0x80;

    c_tuner->tuner_config_ext.cTuner_special_config = 0x01; // RF AGC is disabled
    c_tuner->tuner_config_ext.cChip = Tuner_Chip_ALPS;
    c_tuner->tuner_config_ext.cTuner_AGC_TOP	= 3;
    c_tuner->tuner_config_ext.cTuner_Base_Addr = 0xC2; // C0, C2, C4,C6
    c_tuner->tuner_config_ext.cTuner_Crystal = 4;
    c_tuner->tuner_config_ext.cTuner_Ref_DivRatio = 64;
    c_tuner->tuner_config_ext.cTuner_Step_Freq = 62.5;
    //(Ref_divRatio*Step_Freq)=(80*50)=(64*62.5)=(24*166.7)=(31.25*128)
    c_tuner->tuner_config_ext.wTuner_IF_Freq = 36125;
    //ptrQAM_Tuner.tuner_config_ext.cTuner_Charge_Pump= 0;

    //ptrQAM_Tuner.tuner_config_ext.Tuner_Read			= i2c_read;
    //ptrQAM_Tuner.tuner_config_ext.Tuner_Write			= i2c_write;

    extern INT32 tun_tda18250_init(UINT32 * ptrTun_id, struct QAM_TUNER_CONFIG_EXT * ptrTuner_Config);
    extern INT32 tun_tda18250_control(UINT32 Tun_id, UINT32 freq, UINT32 sym, UINT8 AGC_Time_Const, UINT8 _i2c_cmd);
    extern INT32 tun_tda18250_status(UINT32 Tun_id, UINT8 *lock);
    c_tuner->nim_Tuner_Init = tun_tda18250_init;
    c_tuner->nim_Tuner_Control = tun_tda18250_control;
    c_tuner->nim_Tuner_Status = tun_tda18250_status;	
    c_tuner->tuner_config_ext.i2c_type_id = bI2cType;
*/
    /*config tuner S3202 END ************************************************************************/
    
    return cfg;
}
#endif


struct scart_init_param scart_param =
{
 	I2C_TYPE_SCB1,          //UINT32 i2c_type_id;
	0,                      //UINT32 vcr_plug_pos;
	(UINT32)NULL,           //UINT32 vcr_callback;
	0,                      //UINT16 scart_volume; 	/*0~7.  =0: Mute; =1: -6dB; =2: -3dB; =3: 0dB, =4: 3dB; =5: 6dB; =6: 9dB; =7: 12dB*/
	0x94,                   //reserved3
};


SciCfg sci_config[] =
{
    {SCI_FOR_RS232, 115200, SCI_PARITY_EVEN},
    {SCI_FOR_MDM, 115200, SCI_PARITY_EVEN},
};

I2cCfg i2c_config[6] =
{
    {I2C_TYPE_SCB0, 100000, 1, NULL, NULL},
    {I2C_TYPE_SCB1, 100000, 1, NULL, NULL},  
    //{I2C_TYPE_SCB2, 0, 0, NULL, NULL},     
    {I2C_TYPE_GPIO0, 40000, 1, &gpio_array[GPIO_I2C0_SDA_INDEX], &gpio_array[GPIO_I2C0_SCL_INDEX]},  
    {I2C_TYPE_GPIO1, 100000, 1, &gpio_array[GPIO_I2C0_SDA_INDEX], &gpio_array[GPIO_I2C0_SCL_INDEX]},          
};

#define SYS_I2C_SDA2 64
#define SYS_I2C_SCL2 65

 
BoardCfg* advance_cfg(BoardCfg* cfg)
{
    if(NULL == cfg)
        return NULL;   
    cfg->chip_param.mem_gpio_enabled = FALSE; //shi 3603 not share
    cfg->chip_param.ci_power_ctl_enabled = TRUE;
#if (SYS_NETWORK_MODULE == NET_ALIETHMAC)	    
    cfg->chip_param.ali_ethmac_enabled = TRUE;
#endif
#ifdef DUAL_ENABLE    
    cfg->chip_param.dual_enabled = TRUE;
#endif

#if(defined SHOW_ALI_DEMO_ON_SCREEN)
    cfg->adv_cfg_para.hdcp_disable = TRUE;
#else
    cfg->adv_cfg_para.hdcp_disable = FALSE;
#endif

    cfg->adv_cfg_para.i2c_for_eddc = I2C_TYPE_GPIO1;
    cfg->adv_cfg_para.hdmi_cm_scl = SYS_I2C_SCL2;
    cfg->adv_cfg_para.hdmi_cm_sda = SYS_I2C_SDA2;
#ifdef AUDIO_DESCRIPTION_SUPPORT    
    cfg->adv_cfg_para.audio_description_support = TRUE;
#else
    cfg->adv_cfg_para.audio_description_support = FALSE;
#endif
    cfg->adv_cfg_para.sys_mute_gpio = gpio_array[SYS_MUTE_INDEX].position;
    cfg->adv_cfg_para.ext_mute_mode = MUTE_BY_GPIO;
    cfg->adv_cfg_para.sys_mute_polar = gpio_array[SYS_MUTE_INDEX].polar;
    cfg->adv_cfg_para.snd_output_chip_type =  0;

#ifdef HD_SUBTITLE_SUPPORT    
    cfg->adv_cfg_para.hd_subtitle_support = TRUE;
#else
    cfg->adv_cfg_para.hd_subtitle_support = FALSE;
#endif

    cfg->adv_cfg_para.tve_full_current_mode = FALSE;
    cfg->adv_cfg_para.tve_tbl = tve_table_total;
#if defined(DUAL_VIDEO_OUTPUT_USE_VCAP)    
    cfg->adv_cfg_para.tve_adjust = g_sd_tve_adjust_table;
#endif

#ifdef SUPPORT_PACKET_26
    cfg->adv_cfg_para.ttx_packet_26_support = TRUE;
#else
    cfg->adv_cfg_para.ttx_packet_26_support = FALSE;
#endif
#ifdef TTX_SUB_PAGE
    cfg->adv_cfg_para.ttx_sub_page = TRUE;
#else
    cfg->adv_cfg_para.ttx_sub_page = FALSE;
#endif

#ifdef MULTI_CAS   
    cfg->adv_cfg_para.cas_type = CAS_TYPE;

#ifdef SUPPORT_CAS9
    cfg->adv_cfg_para.cas9_support = TRUE;
#else
    cfg->adv_cfg_para.cas9_support = FALSE;
#endif
    cfg->adv_cfg_para.invert_detect  = 0;
#endif

#ifdef SUPPORT_AFD_SCALE
    cfg->adv_cfg_para.afd_scale_support = TRUE;
#else
    cfg->adv_cfg_para.afd_scale_support = FALSE;
#endif

#ifdef H264_SUPPORT_MULTI_BANK
    cfg->adv_cfg_para.h264_support_mulit_bank = TRUE;
#else
    cfg->adv_cfg_para.h264_support_mulit_bank = FALSE;
#endif
#ifdef CHANCHG_VIDEOTYPE_SUPPORT
    cfg->adv_cfg_para.chanchg_video_type_support = TRUE;
#else
    cfg->adv_cfg_para.chanchg_video_type_support = FALSE;
#endif
#ifdef AVC_SUPPORT_UNIFY_MEM
    cfg->adv_cfg_para.avc_unify_mem_support = TRUE;
#else
    cfg->adv_cfg_para.avc_unify_mem_support = FALSE;
#endif
    cfg->adv_cfg_para.ce_api_enabled = TRUE;
   return cfg;
}

extern INT32 scart_mx9671_attach(struct scart_init_param * param);
extern void pan_ch455_id_set(struct pan_device *dev, UINT32 id);
extern INT32 pan_ch455_attach(struct pan_configuration *config);
BoardCfg* get_board_config(void)
{
    UINT8 i;
    MEMSET(&board_config, 0, sizeof(BoardCfg));
    board_config.pin_mux_count          = ARRAY_SIZE(pin_mux_array);
    board_config.all_gpio_count         = ARRAY_SIZE(gpio_array);
    board_config.mem_gpio_enabled       = MEM_GPIO_ENABLED;
    board_config.pin_mux_array          = pin_mux_array;
    board_config.all_gpio_array         = gpio_array;

    board_config.ddr_power_ctl          = NULL;
    board_config.sys_power              = &gpio_array[SYS_POWER_INDEX];
    board_config.mute                   = &gpio_array[SYS_MUTE_INDEX];        
    board_config.usb_power              = NULL;
    board_config.fp_standby             = NULL;
    board_config.scart_tvsat_switch     = NULL;
    board_config.scart_aspect           = &gpio_array[SCART_ASPACT_GPIO_INDEX];
    board_config.scart_tv_fb            =  &gpio_array[SCART_TV_FB_GPIO_INDEX];   
    board_config.scart_power            = &gpio_array[SCART_TVSTANDBY_GPIO_INDEX];
    board_config.scart_vcr_switch       = NULL;
    board_config.scart_vcr_detech       = NULL;
    board_config.smc_5v_ctl             = &gpio_array[SYS_SMC_SWITCH];
    board_config.ata2lan_cs             = NULL;
#ifdef SDIO_SUPPORT    
    board_config.sdio_detect            = &gpio_array[SDIO_GPIO_DETECT_INDEX];
    board_config.sdio_lock              = &gpio_array[SDIO_GPIO_LOCK_INDEX];
    board_config.sdio_cs                = &gpio_array[SDIO_GPIO_CS_INDEX];
#endif


#ifdef DVBS_SUPPORT
    board_config.front_end_cfg[0] = front_end_s_cfg(0);
#endif
#ifdef ISDBT_SUPPORT
    board_config.front_end_cfg[1] = front_end_isdbt_cfg(1);
#endif
#ifdef DVBT_SUPPORT
    board_config.front_end_cfg[1] = front_end_t_cfg(1);
#endif

#ifdef DVBC_SUPPORT  
    board_config.front_end_cfg[0] = front_end_c_cfg(0);
#endif   
    
    board_config.libc_printf_uart_id = SCI_FOR_RS232;
    board_config.sci_config[0] = &sci_config[0];
#ifdef SEE_CPU    
    board_config.sci_config[1] = &sci_config[1];
#endif    
    for(i=0;i<6;i++)
    {
        board_config.i2c_config[i] = &i2c_config[i];
    }

    board_config.i2c_gpio_num = 3;    //shi   //3;
    board_config.i2c_scb_num = 2;    //shi    //2;   
    
    board_config.scart_param = &scart_param;
    board_config.scart_attach = scart_mx9671_attach;
    
    board_config.pan_config = &pan_config;
    board_config.pan_i2c_id_set = pan_ch455_id_set;
    board_config.pan_i2c_id = I2C_TYPE_GPIO0;
    board_config.pan_attach = pan_ch455_attach;

    board_config.flash_type = 0;
    board_config.rfm_attach = NULL;
    board_config.rfm_i2c_id = I2C_TYPE_SCB1;

    board_config.key_map = g_itou_key_tab;
    board_config.ir_key_maps = ir_key_maps;
    board_config.key_map_cnt = sizeof(g_itou_key_tab)/(sizeof(struct ir_key_map_t));
    return advance_cfg(&board_config);    
}



